A linear feedback shift register (LFSR) is often used to implement a clock signal frequency divider for various applications, including phase lock loop applications. Such LFSR-based clock frequency dividers include a circuit for detecting an invalid state generated by the LFSR and responsively modify the invalid state so that the LFSR generates a valid state. Additionally, such LFSR-based clock frequency dividers include another circuit for detecting an end-of-sequence state generated by the LFSR.
In the past, both the invalid state detecting circuit and end-of-sequence detecting circuit generate signals for an OR gate, whereby the OR gate responsively generates a signal to initiate the changing of the invalid state to a valid state or setting the LFSR to an initial valid state. The additional OR gate introduces delay that adversely impacts the speed of the LFSR-based clock divider. Other impacts to the speed of the LFSR-based clock divider include delays associated with separate multiplexers coupled between adjacent flip-flops of the LFSR, respectively, in order to introduce the initial valid state into the LFSR. The additional multiplexers and OR gate also have the negative consequence of requiring more integrated circuit (IC) footprint to implement, as requiring more power to operate.